The present invention relates to a semiconductor device with spare memory cells.
With the increase in the memory capacity of recent semiconductor memory devices, there is an increasing probability that semiconductor memories will be fabricated containing defective memory cells, although the number may be very small. Technology has been studied and developed which enables the semiconductor memory devices containing defective memory cells to operate as if they didn't contain defective ones. The technology is based on the following idea. Spare memory cells, together with ordinary memory cells, are formed on a chip. When a defective memory cell is addressed, a spare memory cell is selected in place of the defective one using a spare memory cell select circuit having the address of the detective memory cell. The spare memory cell select circuit contains nonvolatile memory cells such as fusible elements for programming the address of the defective memory cell.
In this type of the memory device, spare memory cells are arranged together with a semiconductor memory having a plurality of memory cells (MC-11 to MC-MN) arranged in a matrix. Two ways of arranging the spare memory cells may be considered; the spare memory cells SMC-01 to SMC-ON are arranged on the same row, as shown in FIG. 1, or the spare memory cells SMC-10 to SMC-MO are arranged on the same column, as shown in FIG. 2. In the memory devices shown in FIGS. 1 and 2, the memory cells MC-11 to MC-MN are selected by a column select circuit 2 and a row select circuit 4 in a well known manner. The spare memory cells SMC-01 to SMC-ON shown in FIG. 1 are selected by a spare memory cell select circuit 6. The spare memory cells SMC-10 to SMC-MO shown in FIG. 2 are selected by a spare memory cell select circuit 8.
In the memory device of FIG. 1 or 2, if the memory cell MC-11, for example, is defective, the spare memory cells SMC-01 to SMC-ON or spare memory cells SMC-10 to SMC-MO are used in place of the memory cells MC-11 to MC-1N or memory cells MC-11 to MC-M1. More specifically, when the memory cell MC-11 is selected in the memory device of FIG. 1, the spare memory cell select circuit 6 responds to a control signal from an external control circuit (not shown) and supplies a row select signal to the spare memory cells SMC-01 to SMC-ON, while at the same time supplying an inhibit signal to the row select circuit 4. As a result, the row select signal from the row select circuit 4 is made ineffective. In the memory device shown in FIG. 2, the spare memory cell select circuit 8 receives a control signal from the external control circuit. Responding to the control signal, the select circuit 8 supplies a column select signal to the spare memory cells SMC-10 to SMC-MO and makes the select signal from the column select circuit 2 ineffective.
An ordinary semiconductor memory device with which a plurality of bits are simulataneously read out and written is provided with a plurality of bit memory sections BMS-1 to BMS-i and BMS-(i+1) to BMS-n, as shown in FIG. 3. Each of the memory sections has an M.times.N array of memory cells MC. The bit memory sections BMS-1 to BMS-n are provided with column select circuits 10-1 to 10-n for selecting columns of the bit memory sections. A row select circuit 12 for selecting rows of the bit memory sections BMS-1 to BMS-n is connected between the bit memory sections BMS-i and BMS-(i+1). The semiconductor memory device shown in FIG. 3 is further provided with a spare memory section SBMS containing a spare M.times.N array of memory cells. The row memory cells of the spare memory section SBMS are selected by the row select circuit 12. The column memory cells in the spare memory section SBMS are selected by a column select circuit 10S.
Suppose now that, in the manufacturing stage of the semiconductor memory device, it is detected that one of the bit memory sections BMS-1 to BMS-n, for example, the bit memory section BMS-i includes at least one defective memory cell. In such a case, the column select circuit 10-i, for example, is substantially disconnected from a data line (not shown) to make the column select circuit 10-i ineffective in its column select function. At the same time, the column select circuit 10S is so designed as to have the same address as that of the column select circuit 10-i. Thus, the spare bit memory section SBMS is ready for use in place of the bit memory section BMS-i. With the provision of the bit memory section SBMS, even if defective memory cells are contained in the bit memory section BMS-i in the manufacturing stage, the semiconductor memory device may be operated as if it has no defective memory cells.
For designing the semiconductor memory device shown in FIG. 3 to have a memory capacity of 8 K words.times.8 bits=64 K bits, a great number of spare memory cells, about 8 K cells, are required. When two or more of the bit memory sections BMS-1 to BMS-n contain defective memory cells, the single spare bit-memory section is insufficient to compensate for the defective memory cells of the two or more bit-memory sections. Thus, even if a semiconductor memory device having spare memory cells of 8 K is fabricated, the semiconductor memory device is treated as a defective memory device when defective memory cells are contained in a plurality of bit memory sections, thereby providing a poor production yield.